In the mounting of an integrated circuit package to a printed circuit board, or similar support substrate, there are different methods of providing electrical interconnections between the package input/output (I/O) pads and the substrate pads. Different types of connecting devices can be used, according to the interconnection method and the configuration of the package.
One configuration that is commonly used in IC packages is to have the I/O pads positioned in an area array of contact pads on one surface of the package. The main advantage of the area array packages is the large number of I/O contacts that are provided, because essentially the entire bottom surface of the module or package is used, in comparison with peripheral lead products, which make use only of locations adjacent to the periphery of the package. Area array packages can have either fully or partly populated bottom surfaces with contact pads. These products are assembled to printed circuit boards using established soldering techniques, where one end of the connecting device is soldered to a contact on the package, and the other end to a contact on the printed circuit board.
In the field of area-array interconnections, solder balls and solder columns are the most common connecting devices that are used for soldering IC packages to the surface of the boards. In preparation for surface mounting on a printed circuit board for example, solder balls or solder columns are permanently attached to the IC package, which in turn are permanently attached to the printed circuit board pads by means of soldering. The assembled structure includes a connecting device, for example a solder ball, with two solder joints, one to a contact on the package surface and one to a contact on the printed circuit board surface.
One major restriction of the area array interconnection technology is the reliability of the solder joints. An assembled product is subjected to thermal variations, and significant stresses are transmitted to the solder joints because of the difference in thermal expansion between the printed circuit board and the IC package. This results from the differences in the coefficient of thermal expansion of the board and the package. One method to reduce stress in the solder joints is to increase the compliance or flexibility of the interconnection element. For example, instead of using a solder ball, a well-known solution is to use a solder column as the interconnecting element. Assembled solder ball connections provide short somewhat cylindrical interconnections, compared to solder columns which provide much longer cylindrical connections, typically in the order of three times longer. A longer cylindrical connection is more compliant resulting in lower stress being transmitted to the solder joints.
There are important drawbacks with the use of solder column interconnections. With a significantly longer connection element the inductance of the connection is increased. High inductance creates unwanted electrical noise in electrical packages. It is essential to maintain the inductance as low as possible in today's high speed or high frequency applications in order to optimize the electrical performance of the IC packages. It would be preferable to use connection elements that are more compliant than solder balls, but with a low inductance, equivalent to that resulting from use of solder balls.
Flat leads can be more compliant than cylindrical connections such as balls and columns. In the patent literature are descriptions of the possible use of flat leads in area array packages. U.S. Pat. No. 4,751,199 which issued Jun. 14, 1999 to Phy, entitled “Process of Forming a Compliant Lead Frame for Array-Type Semiconductor Packages”, and U.S. Pat. No. 5,420,461 which issued May 30, 1995 to Mallik et al., entitled “Integrated Circuit Having a Two-Dimensional Lead Grid Array”, teach the use of flat leads on an area array IC package. U.S. Pat. No. 6,339,534, issued Jan. 15, 2002 to Coico et al, entitled “Compliant Leads for Area Array Surface Mounted Components”, shows another example of flat leads used in area-array packages. In this particular case, leads are arranged in a radially-oriented manner with respect to the center of the package, in order to reduce the stress transmitted to the package. Even with flat leads which are more flexible than cylindrical connections, it is preferable to have long leads to achieve stress reduction. The drawback with longer leads is the same as with solder columns, namely, electrical inductance is increased.
In the past, flat leads have been used extensively as interconnecting elements in peripherally connected products such as quad flat packs. In the field of peripheral interconnections, some examples show where duplicated leads are used as the interconnection elements. U.S. Pat. No. 4,867,715, issued Sep. 19, 1989 to Roth et al entitled “Interconnection Lead With Redundant Bonding Regions”, U.S. Pat. No. 4,987,474 which issued Jan. 22, 1991 to Yasuhara et al, entitled “Semiconductor Device and Method of Manufacturing the Same”, U.S. Pat. No. 5,270,492 which issued Dec. 14, 1993 to Fukui, entitled “Structure of Lead Terminal of Electronic Device”, and U.S. Pat. No. 5,647,124 which issued Jul. 15, 1997 to Chan et al, entitled “Method of Attachment of a Semiconductor Slotted Lead to a Substrate” provide examples of the use of flat leads in peripheral connection packages. For today's high density IC packages, peripheral connection packages are not practical as they do not offer a sufficient number of I/O connections, because of the inherent configuration where only the outside peripheral area of the packages is used to connect to the printed circuit card.
Another method to connect an area array package to a printed circuit board is land-grid-array, or spring land-grid-array, that is described in U.S. Pat. No. 6,302,702, issued Oct. 16, 2001, to Audet et al, entitled “Connecting Devices and Method for Interconnections Circuit Components”. This patent describes, connecting devices that are joined to the IC Package which are not soldered to contacts on the surface of the printed circuit boards. Alternatively, interconnections are achieved by compressing the tips of the connecting devices onto the pads of the printed circuit board, by use of compression hardware maintaining the IC package in position on the board. This allows the package to be demountably assembled to the printed-circuit board permitting removal and replacement of the package from the printed-circuit board without need to solder or de-solder the package. In this case, it is advantageous to have relatively long connecting springs, that are thereby more flexible. Longer springs also have some of the same drawbacks as described above, namely electrical inductance is increased if the spring connectors are longer. One configuration offering independent conductors is proposed in this prior art patent which comprises a pair of independently compressible spring arms. One drawback with this approach is the complexity and space required by the independently compressible spring arms.
As we mentioned earlier, the major drawback of increasing the length of the connecting devices is that, with increased length, inductance of the element is drastically increased. Impact of length on the inductance of a conductor is shown by the formula:
      L    self    =      5    ⁢    d    ⁢          {                        ln          ⁡                      (                                                                                2                    ⁢                    d                                                                                                r                                                      )                          -                                            3                                                          4                                          }        ⁢    nH  for a cylindrical conductor of radius r and length d, where r and d are expressed in inches, and L in nano-Henry. (See reference: “Inductance”, by Eric Bogatin, Giga Test Labs, Oct. 3, 2002)
From this formula, we see that if we have, for example, a conductor of 0.01 inches in diameter, increasing the length from 0.05 inches to 0.10 inches will increase the inductance by about three folds. This increase in inductance will have a negative impact on the switching noise of the IC package.
Many of the connecting devices shown in the prior art are a compromise between flexibility and inductance. If the connecting device is longer, it may be more flexible, but it will be more inductive.
One method of reducing inductance in IC device to package interconnections is to use more than one electrical conductor attached on each pad of the device, as well as on the package. This method is used in wire-bonded interconnections, as shown in U.S. Pat. No. 4,686,492, issued Aug. 11, 1987 to Grellman et al., entitled “Impedance Match Connection Using Multiple Layers of Bond Wires”, U.S. Pat. No. 6,215,670, issued Apr. 10, 2001 to Khandros, entitled “Method for Manufacturing Raised Electrical Contact Pattern of Controlled Geometry”, and U.S. patent application Ser. No. 2001/0015490, published Aug. 23, 2001 to Lee, entitled, “High Speed Digital and Microwave Device Package”. All of these methods have the drawback of requiring the attachment of more than one wire bond on each of the pads of the IC device, and is not usable for area-array package interconnections.
Thus, as shown by this description of the prior art, it is apparent that there is a need for a flexible, but still low-inductance connecting device or connector for use in area-array packages, for use in surface-mounted soldered assemblies, as well as for land-grid-array, or demountable assemblies.